DSPIC30F4011-30I/ML【PDF 70/238 页】IC DSPIC MCU/DSP 48K 44QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1917

66页 67页 68页 69页 [70页]71页 72页 73页 74页

2010 Microchip Technology Inc.

DS70135G-page 161

dsPIC30F4011/4012

21.4

Watchdog Timer (WDT)

21.4.1

WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software

malfunction. The WDT is a free-running timer that runs

off an on-chip RC oscillator, requiring no external

component. Therefore, the WDT timer continues to

operate even if the main processor clock (e.g., the

crystal oscillator) fails.

21.4.2

ENABLING AND DISABLING

THE WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register, FWDT.

Setting FWDTEN = 1 enables the Watchdog Timer.

The enabling is done when programming the device.

By default, after chip erase, FWDTEN bit = 1. Any

device

programmer

capable

programming

dsPIC30F devices allows programming of this and

other Configuration bits.

If enabled, the WDT increments until it overflows or

“times out”. A WDT time-out forces a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

If a WDT times out during Sleep, the device wakes-up.

The WDTO bit in the RCON register is cleared to

indicate a wake-up resulting from a WDT time-out.

Setting FWDTEN = 0 allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

21.5

Power-Saving Modes

There are two power-saving states that can be entered

through the execution of a special instruction, PWRSAV.

These are: Sleep and Idle.

The format of the PWRSAV instruction is as follows:

PWRSAV <parameter>

where,

‘parameter’ defines Idle or Sleep mode.

21.5.1

SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is

shut down. If an on-chip oscillator is being used, it is

shut down.

The Fail-Safe Clock Monitor is not functional during

Sleep, since there is no clock to monitor. However, the

LPRC clock remains active if WDT is operational during

Sleep.

The Brown-out Reset protection circuit and the Low-

Voltage Detect (LVD) circuit, if enabled, remain

functional during Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

Any interrupt that is individually enabled and

meets the required priority level

Any Reset (POR, BOR and MCLR)

WDT time-out

On waking up from Sleep mode, the processor restarts

the same clock that was active prior to entry into Sleep

mode.

When

clock

switching

enabled,

bits

COSC<1:0> determine the oscillator source to be

used on wake-up. If clock switch is disabled, then

there is only one system clock.

If the clock source is an oscillator, the clock to the

device is held off until OST times out (indicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1 (indicating that the PLL is

stable). In either case, TPOR, TLOCK and TPWRT delays

are applied.

If EC, FRC, LPRC or ERC oscillators are used, then a

delay of TPOR (~10

μs) is applied. This is the smallest

delay possible on wake-up from Sleep.

Moreover, if the LP oscillator was active during Sleep,

and LP is the oscillator used on wake-up, then the start-

up delay is equal to TPOR. PWRT and OST delays are

not applied. In order to have the smallest possible start-

up delay when waking up from Sleep, one of these

faster wake-up options should be selected before

entering Sleep.

Note:

If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<1:0>

and FPR<3:0> Configuration bits.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式